Several types of non-volatile semiconductor latches are known in the prior art. They use different kind of non-volatile memory elements like fuses, MNOS transistors, EPROM transistors, standard EEPROM transistors, Flash EEPROM transistors, etc. Normally the transistor memory elements need a programming voltage relatively higher than the normal power supply. For many technological processes this means that almost all transistors in the non-volatile latch have to be made by high-voltage (HV) transistors instead of normal low-voltage (LV) transistors. As a result, the non-volatile latch area, a critical parameter, may increase a lot in size.
Additional problems exist in the non-volatile latches using hot-electron injection devices like EPROM and Flash EEPROM transistors. Normally they need a large current for programming, for example 0.5 to 1.0 mA/bit, in contrast to the standard EEPROM transistors using Fowler-Nordheim tunnel injection which takes, for example about 10 pA/bit. So, a disposal of hot-electron injection devices in a non-volatile latch, for example in the way described in GB-A 2 054 303 (“Hughes”), will require a large programming current flowing though the data line, respectively very large transistors along the drain programming path of the hot-electron injection devices. This will cause an additional increase of the non-volatile latch area and the area of its periphery.
In Hughes, the WHOLE non-volatile element, IGFET Q3, is included in the complementary driver (Q3, Q5—FIG. 1) or in the complementary load (Q1, Q3—FIG. 5). The same applies for the IGFET Q4 in the other branch. In the embodiments the non-volatile element (cell) is split in two parts—a read transistor and a program transistor. Only the read transistor T5 is included in the complementary driver (T1, T5—FIG. 1). The same applies for T6 in the other branch. The other part of the non-volatile element (cell) in the embodiments, the program transistor T7, is not included in the complementary driver (compare to GB 2 054 303, there CLAIMS, lines 46 to 49). The same applies for T8 in the other branch.
In Hughes the input data for programming the non-volatile (NV) latch are provided through a WRITE transistor Q9 (and Q11 in FIGS. 3 and 4) and applied to the respective nodes X (and Y in FIGS. 3 and 4). In the embodiments the input data for programming of the NV latch are applied on the drain of the program transistors T7 and T8, therefore the input data are decoupled from the respective output nodes Q and Q|(quer).
In Hughes the NV-latch is programmed by applying a high voltage (HV) on the control gate of the transistors Q3 or Q4 (See FIGS. 1 and 5), i.e. on the respective nodes X or Y. (See also rows 56 to 61 of the patent background). It means that all transistors (except Q10 and Q12) of this latch may be put under HV during programming. In the embodiments the NV latch is programmed by applying HV only on the node 19 (see FIGS. 1 and 3). Therefore the HV is decoupled from the respective output nodes Q and Q| and only the gates of the program transistors T7 and T8 are put under HV during programming.
In Hughes the NV-latch needs buffers (Q7, Q8) and/or READ transistors (Q10, Q12) between the respective nodes X and Y from one side and the DATA line from other side. (See also rows 53 to 56 of the claims). In the embodiments the NV latch nodes Q and Q| can be used directly as respective NV latch outputs.
The above-listed problems are solved by U.S. Pat. No. 5,428,571 to Atsumi et al. (“Atsumi”), which discloses splitting the hot-electron injection device into two parts: A reading transistor and a writing transistor with a common floating gate. But a limitation of this design solution is the use of depletion transistors that are not available in each process. Another limitation of this approach is that the threshold voltage of the depletion-type reading transistor has to be increased to positive values to avoid a static current in the non-volatile latch. This leads to strong requirements to the latch programming and decreases the data retention time of the latch.
In Atsumi the reading transistor (T4, all Figures) is depletion type (see also claims 1 and 12) whereas the writing transistor (T3, all Figures) is enhancement type. In the embodiments both the read transistor (T5, T6) and the program transistor (T7, T8) are enhancement type.
In Atsumi the NV latch needs additional protection means like the depletion transistor T2 (see also claims 1 and 12). In the embodiments the NV latch does not need such protection means. There is no depletion transistor at all in the proposed NV latch.
In Atsumi, the reading and the writing transistors have got a common control gate connected to Vpp/Vss (FIGS. 1, 2, 4 and 5). Only in FIG. 3 a variant with two control gates is shown but the control gate of the reading transistor T4 is connected to ground (Vss). In the embodiments the non-volatile cell (T5, T7) has got two separate control gates. The control gate of the read transistor T5 is connected to the respective output node Q|. The same for the other memory cell (T6, T8).
A Comparison between the inventive embodiments and U.S. Pat. No. 4,399,522 to Kotecha (“Kotecha”) is as follows. In Kotecha, the non-volatile element 12 (FIG. 1) used in the RAM cell is ONE transistor with common drain 34, common source 36, common floating gate 24 and two control gates (30 and 46). The same applies for the other non-volatile element 14. Also in the inventive embodiments “a said transistor (i.e. one transistor) having first and second control gates, a floating gate”. In the embodiments the non-volatile element (cell) used in the NV latch consists in fact of TWO transistors (T5 and T7) with only common the floating gate 13. In could be seen in all Figures that the drain (Q), the source (21) and the control gate (15) of T5 are different from the drain (D), the source (ground) and the control gate (17) of T7. The same for the non-volatile element (cell) used in the other branch—it also consists of TWO separate transistors T6 and T8 with only common the floating gate 14.